1. Field of Invention
The present invention relates to a method for fabricating a semiconductor device. More particularly, the present invention relates to a method for fabricating a memory having a memory area and a periphery area.
2. Description of Related Art
As the development of semiconductor technology advances for increasing the integration of semiconductor devices, the line width of the semiconductor devices must be reduced. Consequently, a variety of problems arise as the size of the cell of the memory device is miniaturized. For example, as the line width of the memory device reduced, the channel length between the source and the drain is correspondingly reduced leading to a short channel effect. The short channel effect is a result of the reduction in the threshold voltage and the increase in the sub-threshold current.
Conventionally, a memory involves integrating memory cell arrays and logic circuit elements onto a single chip. The logic circuit elements may include high voltage devices and low voltage devices. The prior art method involves first forming an tunnel oxide layer and a first polysilicon layer in the memory array area, followed by forming the buried diffusion regions in the substrate adjacent to the tunnel oxide layer and the first polysilicon layer. Thereafter, an inter-gate dielectric layer, for example an oxide-nitride-oxide (ONO) film, is formed on the first polysilicon layer. Subsequently, thermal oxidation processes are respectively performed to form the gate insulating layers for the high voltage devices and the low voltage devices in the logic circuit area. A second conductive layer is eventually formed over the inter-gate dielectric layer, followed by patterning the second conductive layer and inter-gate dielectric layer and the first conductive layer in the memory array area to form an array of memory cells.
Accordingly, subsequent to the formation of the buried diffusion region in the semiconductor substrate, the high thermal budget processes, such as the fabrication process of the thick gate insulating layers for the high voltage devices, can seriously affect the size of the buried diffusion region. In essence, the high temperature in the thermal processes leads to an expansion of the buried diffusion region. Consequently, the short channel effect is acerbated and the device characteristics of the memory are difficult to control.
Moreover, in the conventional manufacturing process of a memory, it is customary to perform a series of process steps subsequent to the fabrication of the inter-gate dielectric layer and before the fabrication of the control gate layer. The inter-gate dielectric layer can potentially be damaged induced in other process steps. Consequently, the quality of the device is compromised.